The present invention is directed to cathode-ray-tube flyback circuits and in particular to those of the type required by high-resolution displays.
In a cathode-ray tube (a "CRT"), the position of the electron beam on the screen is determined by the current that flows through deflection yokes. FIG. 1 is a simplified schematic diagram of the type of circuit typically employed to control yoke current. The yoke L.sub.y is shown connected to a fixed source voltage V.sup.+ at one end and through a switch S to ground at the other. A diode D and capacitor C are connected in parallel with the switch S. The drawing includes a conceptual diode D.sub.s to indicate that the switch S is a unidirectional electronic switch. A gating signal V.sub.g controls the state of the switch S.
FIGS. 2a-d illustrate the operation of this conventional circuit. The operation is cyclical, and FIGS. 2a-d enter the cycle at a time t.sub.0 at which the gating signal assumes an actuation value V.sub.on. FIG. 2a represents the value of the gating signal.
FIG. 2b depicts the yoke current. For reasons that will become apparent as the description proceeds, the current flow through the yoke is negative at time t.sub.0 ; i.e., the current flows toward the positive source terminal. Diode D therefore conducts, clamping one end of the yoke L.sub.y to ground. Because a fixed voltage V.sup.+ is applied across the yoke L.sub.y at this time, the yoke current increases linearly, and the horizontal position of the beam accordingly moves across the CRT screen to produce the forward, visible trace. As FIG. 2b shows, the yoke current becomes positive at time t.sub.1, so the yoke current stops flowing through the diode D and starts flowing through the switch S at that time.
At time t.sub.2, the gating signal V.sub.g assumes a ground-level, disabling value, and the switch S responds after a delay by beginning to open at time t.sub.3. As is illustrated by FIG. 2c, which depicts the switch current, the switch S is completely open after a delay t.sub.d. This begins the horizontal retrace.
Specifically, the yoke current begins to flow through the capacitor C when the switch S opens. The voltage on capacitor C accordingly rises. FIG. 2d depicts the capacitor voltage. The capacitance of capacitor C is low enough that the voltage rise is rapid; the purpose of capacitor C is to reverse the yoke current during the horizontal retrace time, and it is preferable to keep the retrace time low.
The resulting waveform of the current through the yoke L.sub.y between times t.sub.3 and t.sub.4 is one-half cycle of a short-period sinusoid. When the yoke current becomes negative, the voltage on capacitor C decreases, reaching zero at time t.sub.4, as FIG. 2d illustrates.
After the capacitor voltage reaches zero at time t.sub.4, the diode D becomes forward biased, clamping the lower end of the yoke to ground and thereby causing a fixed voltage across the yoke. The yoke current therefore increases linearly from a negative value. During this linear increase, the gating signal V.sub.g returns to the activation value V.sub.on that it assumed at time t.sub.0, and the cycle repeats.
The foregoing discussion is equally applicable both to conventional CRTs and to high-resolution CRTs. For high-resolution CRTs, however, the design constraints on circuit components are more stringent.
Increased CRT resolution means an increased number of horizontal scans for each vertical scan. Moreover, to avoid flicker, the vertical scan rate in higher-resolution displays is typically higher than that in conventional television. It is at least 60 Hz and preferably 66 Hz or even 80 Hz. The horizontal scan frequency is therefore much higher than the 15.75 kHz American television standard; it is typically at least 64 kHz and can exceed 100 kHz. The retrace time (t.sub.fly) must therefore be shortened from the 11 microseconds common in conventional television to a value in the range of 1.5-3.0 microseconds. This means that the peak capacitor voltage--and thus the voltage that the electronic switch can withstand--must increase. Additionally, field-effect transistors ("FETs") are the transistors of choice for such applications, and, for a given chip size, the on resistances of FETs increase faster than the squares of their breakdown voltages. The resultant resistance can detract from the linearity of the yoke-current curve.
One solution to this problem has been to configure the switch as a plurality of transistors connected in series; the total voltage that such a switch can withstand is proportional to the number of transistors, and the total switch resistance increases only linearly with the required voltage. Although this approach has been followed with some success, a certain degree of switch complexity has heretofore resulted from the requirement that the different switch transistors, which are at widely different potentials in the off state, be controlled by a common gate signal.
FIG. 3 depicts a typical prior-art circuit that illustrates this complexity. A series combination of capacitors C1 and C2 embodies the current-reversing capacitor C of FIG. 1, while the switch corresponding to switch S of FIG. 1 includes transistors Q1 and Q2 as well as the remaining circuitry in FIG. 3, which enables transistors Q1 and Q2 to respond to a common gating signal.
As will be explained presently, a high signal at terminal 12 causes transistors Q1 and Q2 to conduct. The conduction of transistor Q2 completes a current path to ground from a supply node 14 through a resistor R1, a diode D1, and the parallel combination of a zener diode D2 and a capacitor C3. As a result, the capacitor C3 is charged to the zener voltage and can be thought of as acting as a voltage supply that imposes a voltage between "supply rails" 16 and 18.
The high signal at the common gating terminal 12 causes current to flow through resistor R2, diode D3, and resistor R3 and forward biases a further diode D4 so as to bias a pnp transistor Q3 to its non-conducting state. The result is a low-voltage output of a voltage divider R5 and R6, and this low voltage prevents transistor Q4 from conducting. The resultant high voltage at the collector of transistor Q4 keeps transistor Q5 turned off and thereby isolates the gate of transistor Q1 from the lower "rail" 18 while permitting conduction through transistor Q6. Transistor Q6 thus provides a path from the high "rail" 16 through resistor R4 and transistor Q6 to the gate of transistor Q1, which accordingly conducts.
Similar circuitry causes transistor Q2 to conduct. There is thus very little potential difference between ground and the drain of transistor Q1, so the voltage across the series combination of capacitors C1 and C2 is nearly zero.
To turn transistors Q1 and Q2 off and thus open the switch, the signal at the common gating terminal 12 assumes a low, disablement value and thus allows the voltage across resistor R3 to drop low enough to turn on transistor Q3. The resultant voltage output from voltage divider R5 and R6 turns on transistor Q4, whose resultant low collector voltage reverses the states of capacitors Q5 and Q6 so that the base of Q1 now becomes isolated from the upper "rail" 16 and has its gate-to-source charge drawn off by transistor Q5. Transistor Q1 thus stops conducting.
By a similar mechanism, transistor Q2 also turns off, so capacitors C1 and C2 are allowed to charge rapidly. The junction of capacitors C1 and C2 is connected to that of transistors Q1 and Q2 so that the switch voltage is divided evenly between the transistors if the capacitances of capacitors C1 and C2 are equal. Consequently, no individual transistor is required to withstand the total switch voltage.
As capacitor C2 charges, the voltage at the lower "rail" 18 rises rapidly above those at the gating and supply terminals 12 and 14. However, diodes D1 and D3 isolate the power and gating terminals 14 and 12 from this high voltage, while capacitor C3 keeps the upper "rail" 16 at the level required to provide the necessary bias voltages for the various devices in the illustrated gate circuitry. The transistors thus remain non-conducting until the gating signal again assumes its activation value.
A couple of observations are in order concerning the circuitry of FIG. 3. The first is that the switch transistor circuit within dashed lines 19 is a four-terminal device; in addition to the control and power terminals--i.e., the base of transistor Q3 and the gate and drain of transistor Q1--circuit 19 includes a supply terminal ("rail" 16) to receive power to provide bias voltages. Although this terminal is effectively isolated during the off state of transistor Q1, it must be connected during the on state to recharge capacitor C3.
The second observation is that the relative complexity of the gate circuit not only has the potential for introducing delay but can also introduce differences between the turn-off times of the switch transistors. This can extend the switch turn-off time t.sub.d (FIG. 2c) and thus extend the retrace time and increase timing uncertainty.